mirror of
https://github.com/XunilGroup/XunilOS.git
synced 2026-06-02 11:44:24 +02:00
csd4ni3l
f943cf5426
removing O(n) operations (ready and sleep queues now), caching timer ticks per irq on init_interrupts aarch64, only saving context when switching, add kill syscall and use it for exit, only push input to init, fix accidental REL_X events drop with virtio, fix the possibility of not having a process to switch to by either staying, switching or idling, improve scheduler by removing double locking and splitting code to multiple functions, do not switch every IRQ but only 100 IRQs, improve rust app building, move x86_64 kernel fb so it doesn't hit heap, update submodules
246 lines
6.8 KiB
Rust
246 lines
6.8 KiB
Rust
use core::arch::asm;
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use x86_64::instructions::tlb::flush_all;
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use crate::{
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arch::arch::safe_lock,
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arch::x86_64::gdt::{GDT, TSS_MUTEX},
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task::context::UserContext,
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task::process::ProcessState,
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task::scheduler::{SCHEDULER, current_pid},
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};
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const IA32_EFER: u32 = 0xC0000080;
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const IA32_EFER_SCE: u64 = 1; // system call enable bit
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const IA32_STAR: u32 = 0xC0000081;
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const IA32_LSTAR: u32 = 0xC0000082;
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const IA32_FMASK: u32 = 0xC0000084;
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const IA32_KERNEL_GS_BASE: u32 = 0xC0000102;
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const IA32_GS_BASE: u32 = 0xC0000101;
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#[repr(C)]
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pub struct PerCpuData {
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pub user_rsp: u64,
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pub kernel_rsp: u64,
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}
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pub static mut PER_CPU: PerCpuData = PerCpuData {
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user_rsp: 0,
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kernel_rsp: 0,
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};
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pub unsafe fn wrmsr(msr: u32, value: u64) {
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let low = value as u32;
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let high = (value >> 32) as u32;
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unsafe {
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asm!(
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"wrmsr",
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in("ecx") msr,
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in("eax") low,
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in("edx") high,
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);
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}
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}
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pub unsafe fn rdmsr(msr: u32) -> u64 {
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let low: u32;
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let high: u32;
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unsafe {
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asm!(
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"rdmsr",
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in("ecx") msr,
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lateout("eax") low,
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lateout("edx") high,
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);
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}
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((high as u64) << 32) | (low as u64)
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}
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pub fn init_syscalls() {
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unsafe {
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flush_all();
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let efer = rdmsr(IA32_EFER);
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wrmsr(IA32_EFER, efer | IA32_EFER_SCE); // enable syscalls
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let per_cpu_addr = &raw const PER_CPU as u64;
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wrmsr(IA32_KERNEL_GS_BASE, per_cpu_addr); // per-cpu kernel data
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asm!("mov gs, ax", in("ax") 0u16);
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if let Some(tss) = TSS_MUTEX.lock().as_ref() {
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PER_CPU.kernel_rsp = tss.privilege_stack_table[0].as_u64();
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}
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#[allow(function_casts_as_integer)]
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wrmsr(IA32_LSTAR, syscall_entry as u64); // set syscall entry function
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wrmsr(IA32_FMASK, 1 << 9); // Mask interupts during syscalls
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wrmsr(IA32_GS_BASE, 0);
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let kernel_cs = (GDT.1.0.0 & !0b11) as u64;
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let user_ds = (GDT.1.3.0 & !0b11) as u64;
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let sysret_base = user_ds - 8;
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let star = (kernel_cs << 32) | (sysret_base << 48);
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wrmsr(IA32_STAR, star);
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}
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}
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#[unsafe(naked)]
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#[unsafe(no_mangle)]
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unsafe extern "C" fn syscall_entry() {
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core::arch::naked_asm!(
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r#"
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swapgs
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mov gs:[0], rsp
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mov rsp, gs:[8]
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sub rsp, 144
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mov qword ptr [rsp + 0], r15
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mov qword ptr [rsp + 8], r14
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mov qword ptr [rsp + 16], r13
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mov qword ptr [rsp + 24], r12
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mov qword ptr [rsp + 32], r11
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mov qword ptr [rsp + 40], r10
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mov qword ptr [rsp + 48], r9
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mov qword ptr [rsp + 56], r8
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mov qword ptr [rsp + 64], rsi
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mov qword ptr [rsp + 72], rdi
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mov qword ptr [rsp + 80], rbp
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mov qword ptr [rsp + 88], rdx
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mov qword ptr [rsp + 96], rcx
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mov qword ptr [rsp + 104], rbx
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mov qword ptr [rsp + 112], rax
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mov rax, qword ptr gs:[0]
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mov qword ptr [rsp + 120], rax
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mov rax, qword ptr [rsp + 96]
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mov qword ptr [rsp + 128], rax
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mov rax, qword ptr [rsp + 32]
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mov qword ptr [rsp + 136], rax
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mov rbx, rsp // rbx = frame base
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// ctx_save(frame)
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mov rdi, rbx
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lea rsp, [rbx - 8]
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call ctx_save
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mov rsp, rbx
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sti
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mov rdi, qword ptr [rbx + 112]
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mov rsi, qword ptr [rbx + 72]
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mov rdx, qword ptr [rbx + 64]
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mov rcx, qword ptr [rbx + 88]
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mov r8, qword ptr [rbx + 40]
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mov r9, qword ptr [rbx + 56]
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lea rsp, [rbx - 24]
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mov rax, qword ptr [rbx + 48]
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mov qword ptr [rsp + 0], rax
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call syscall_dispatch
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mov rsp, rbx
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mov qword ptr [rbx + 112], rax
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mov rdi, rbx
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lea rsp, [rbx - 8]
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call ctx_save
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mov rsp, rbx
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mov rdi, rbx
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call syscall_yield_check
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mov rax, qword ptr [rsp + 128]
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mov qword ptr [rsp + 96], rax
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mov rax, qword ptr [rsp + 136]
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mov qword ptr [rsp + 32], rax
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// restore registers from frame
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mov rax, qword ptr [rsp + 112]
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mov rbx, qword ptr [rsp + 104]
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mov rcx, qword ptr [rsp + 96]
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mov rdx, qword ptr [rsp + 88]
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mov rbp, qword ptr [rsp + 80]
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mov rdi, qword ptr [rsp + 72]
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mov rsi, qword ptr [rsp + 64]
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mov r8, qword ptr [rsp + 56]
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mov r9, qword ptr [rsp + 48]
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mov r10, qword ptr [rsp + 40]
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mov r11, qword ptr [rsp + 32]
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mov r12, qword ptr [rsp + 24]
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mov r13, qword ptr [rsp + 16]
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mov r14, qword ptr [rsp + 8]
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mov r15, qword ptr [rsp + 0]
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cli
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mov rsp, qword ptr gs:[0]
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swapgs
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sysretq
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.done:
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ud2
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"#,
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);
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}
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#[unsafe(no_mangle)]
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unsafe extern "C" fn syscall_yield_check(_ctx: *mut UserContext) {
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if let Some(pid) = current_pid() {
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let needs_yield = {
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let guard = safe_lock(|| SCHEDULER.lock());
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guard
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.processes
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.get(&pid)
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.map_or(false, |p| !matches!(p.state, ProcessState::Running))
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};
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if needs_yield {
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SCHEDULER.switch_next(true);
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}
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}
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}
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#[unsafe(naked)]
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#[unsafe(no_mangle)]
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pub unsafe fn run_next(ctx: *const UserContext, user_rsp: u64, user_cs: u64, user_ss: u64) {
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core::arch::naked_asm!(
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// rdi = ctx, rsi = user_rsp, rdx = user_cs, rcx = user_ss
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"mov gs:[0], rsi",
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"mov rax, rcx",
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"and eax, 0xFFFC",
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"mov ds, ax",
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"mov es, ax",
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// save ctx ptr on stack, then build iret frame
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"push rdi",
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"push rcx",
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"push rsi",
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"push qword ptr [rdi + 136]",
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"push rdx",
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"push qword ptr [rdi + 128]",
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// load all gp regs via rdi
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"mov r15, qword ptr [rdi + 0]",
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"mov r14, qword ptr [rdi + 8]",
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"mov r13, qword ptr [rdi + 16]",
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"mov r12, qword ptr [rdi + 24]",
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"mov r11, qword ptr [rdi + 32]",
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"mov r10, qword ptr [rdi + 40]",
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"mov r9, qword ptr [rdi + 48]",
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"mov r8, qword ptr [rdi + 56]",
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"mov rsi, qword ptr [rdi + 64]",
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"mov rbp, qword ptr [rdi + 80]",
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"mov rdx, qword ptr [rdi + 88]",
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"mov rcx, qword ptr [rdi + 96]",
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// ctx_ptr is at [rsp + 40]
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"mov rax, qword ptr [rsp + 40]",
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"mov rbx, qword ptr [rax + 104]",
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"mov rdi, qword ptr [rax + 72]",
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"mov rax, qword ptr [rax + 112]",
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"swapgs",
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"iretq",
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);
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}
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